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(parent: 5dc2065) | patch
i965/vec4: do not trim dead channels on gen6 for math
authorTapani Pälli <tapani.palli@intel.com>
Wed, 2 Apr 2014 08:46:58 +0000 (11:46 +0300)
committerTapani Pälli <tapani.palli@intel.com>
Wed, 2 Apr 2014 16:50:48 +0000 (19:50 +0300)
commite14cc504f307a7fa88c8b6757df53026aaa39b08
tree23982c473a15ae5bd27210bc650dd832e3f93e4etree
parent5dc206525b6ff799870f880469a985f3d944eb77commit | diff
i965/vec4: do not trim dead channels on gen6 for math

Do not set a writemask on Gen6 for math instructions, those are
executed using align1 mode that does not support a destination mask.

v2: cleanups, better comment (Matt)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76883

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
src/mesa/drivers/dri/i965/brw_vec4.cpp diff | blob | history