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(parent: 8ce6839) | patch
introduce conversion output object (prevents file IO in FHDL backends)
authorSebastien Bourdeauducq <sb@m-labs.hk>
Wed, 8 Apr 2015 12:28:23 +0000 (20:28 +0800)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Wed, 8 Apr 2015 12:28:23 +0000 (20:28 +0800)
commite1702c422c8141c4010eef0c61f8099825512d82
tree97162639aacc07dd16a27f49ceaca1aeba263f14tree
parent8ce683964ac55cad51e01b5f152f4bbe3a190038commit | diff
introduce conversion output object (prevents file IO in FHDL backends)
mibuild/altera/quartus.py diff | blob | history
mibuild/generic_platform.py diff | blob | history
mibuild/lattice/diamond.py diff | blob | history
mibuild/sim/verilator.py diff | blob | history
mibuild/xilinx/ise.py diff | blob | history
mibuild/xilinx/vivado.py diff | blob | history
migen/fhdl/conv_output.py [new file with mode: 0644] blob
migen/fhdl/edif.py diff | blob | history
migen/fhdl/specials.py diff | blob | history
migen/fhdl/verilog.py diff | blob | history