Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
authorEddie Hung <eddie@fpgeh.com>
Mon, 27 Jan 2020 22:02:13 +0000 (14:02 -0800)
committerEddie Hung <eddie@fpgeh.com>
Mon, 27 Jan 2020 22:02:13 +0000 (14:02 -0800)
commite18aeda7ed3b3dbf4700e25c2bc745c93541b3b8
treef41b454d90ffdff2f08a625cf36932805f3ee8d8
parentcfb0366a18b0f3cab254636fdf534a3de76af8d5
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards

Just like Verilog...
passes/pmgen/ice40_wrapcarry.cc
techlibs/ice40/ice40_opt.cc