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(parent: c1872c5) | patch
rename l2FrontendBus as fsb
authorYunsup Lee <yunsup@sifive.com>
Sat, 25 Mar 2017 04:38:31 +0000 (21:38 -0700)
committerYunsup Lee <yunsup@sifive.com>
Sat, 25 Mar 2017 04:38:31 +0000 (21:38 -0700)
commite2073feef87f080ac3e354774c3a0cbb0a55be3d
tree4bd9bcad58b2679d8c969ff85b49a557fec0583ftree
parentc1872c574b1e471778ec28e6a782b6547e6917dacommit | diff
rename l2FrontendBus as fsb
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala diff | blob | history
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