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(parent: 2919adf) | patch
i965/gen10: Change the order of PIPE_CONTROL and load register.
authorRafael Antognolli <rafael.antognolli@intel.com>
Wed, 8 Nov 2017 19:39:52 +0000 (11:39 -0800)
committerRafael Antognolli <rafael.antognolli@intel.com>
Fri, 1 Dec 2017 19:27:27 +0000 (11:27 -0800)
commite20830db96f744f326a995541da1fcafaa3f96ff
tree61ed792799c1a93aa3041156645d3b477b9fbe5btree
parent2919adffe9f8ac4ea9e152db45c410cdc4514b7dcommit | diff
i965/gen10: Change the order of PIPE_CONTROL and load register.

I believe the workaround describes that the MI_LOAD_REGISTER_IMM should
come right after the 3DSTATE_SAMPLE_PATTERN.

This fixes GPU hangs in the i965 initial state batchbuffer when running
some Piglit tests with always_flush_batch=true.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/gen8_multisample_state.c diff | blob | history