intel/isl/gen4: Make depth/stencil buffers Y-Tiled
authorNanley Chery <nanley.g.chery@intel.com>
Mon, 16 Jul 2018 22:42:39 +0000 (15:42 -0700)
committerNanley Chery <nanley.g.chery@intel.com>
Thu, 19 Jul 2018 18:05:07 +0000 (11:05 -0700)
commite2e32b6afd4cd1cd091877b638288e861a537760
tree2fa802bd24029ce1e561a5dc9add539e49de9580
parent44ab26d0c9bd95f8d15ead5b92f743ee13296aef
intel/isl/gen4: Make depth/stencil buffers Y-Tiled

Rendering to a linear depth buffer on gen4 is causing a GPU hang in the
CI system. Until a better explanation is found, assume that errata is
applicable to all gen4 platforms.

Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e
("i965/miptree: Share tiling_flags in miptree_create").

Reported-by: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107248
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/intel/isl/isl_gen4.c