Added init= attribute for fpga-style reset values
authorClifford Wolf <clifford@clifford.at>
Wed, 20 Nov 2013 00:49:37 +0000 (01:49 +0100)
committerClifford Wolf <clifford@clifford.at>
Wed, 20 Nov 2013 00:49:37 +0000 (01:49 +0100)
commite340532ce5d60129fbfb2e1b0a3eb916ec856b26
tree5aed3e9da1417ba879fd8543290133deacf46e54
parenta1353ec61b00442bb5ebe9f30408324b89cf6a82
Added init= attribute for fpga-style reset values
README
frontends/verilog/parser.y