dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Fri, 8 Mar 2019 10:47:02 +0000 (10:47 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 27 Mar 2019 13:29:10 +0000 (13:29 +0000)
commite36839e7780df11065ab0a08abaf3fcf68135aa7
tree99b2cc04c0407bb48789f070a454662ec757a943
parent9059aafbd3157f515d23b7ba5e89a2d1a8cfd41a
dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)

For SGIs and PPIs:
* When ARE is 1 (only value supported in gem5) for the Security state of
an interrupt, the field for that interrupt is RES0 and an implementation
is permitted to make the field RAZ/WI in this case.

Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
src/dev/arm/gic_v3_distributor.cc