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(parent: 4c96611) | patch
build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 19 Nov 2018 11:50:07 +0000 (12:50 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 19 Nov 2018 11:50:07 +0000 (12:50 +0100)
commite3c6bd58466c4d9f8bb3684383bb72673d4c3783
tree80473efb37c6715847544ff3a971cefe88853537tree
parent4c966114f87dda4af485f6b6adac4fbd2d3d6fe3commit | diff
build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools
litex/build/microsemi/libero_soc.py diff | blob | history