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(parent: 2f52d36) | patch
gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 16 Nov 2015 15:18:09 +0000 (16:18 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 16 Nov 2015 15:18:09 +0000 (16:18 +0100)
commite407a1cddaf424ba902fb97bda8962fe93a421e5
tree2770d4efb564fcbfcd7209415f244192bba5dba6tree
parent2f52d364affc6f5483ff8c3e635f0469abe7525acommit | diff
gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal and blocking_assign
litex/gen/fhdl/verilog.py diff | blob | history