git.libre-soc.org Git - gem5.git/commit

author	Gabe Black <gblack@eecs.umich.edu>
	Sun, 5 Aug 2007 03:12:54 +0000 (20:12 -0700)
committer	Gabe Black <gblack@eecs.umich.edu>
	Sun, 5 Aug 2007 03:12:54 +0000 (20:12 -0700)
commit	e410a925df8d37f386c97dc7cdd9a78347ce4700
tree	b4102987453b1303051dfeea61aa1a45c2e5e75f	tree
parent	ced6cbcccf4540358093f060dad4d59ad6557d6a	commit \| diff

X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9

29 files changed:

src/arch/x86/emulenv.cc		diff \| blob \| history
src/arch/x86/emulenv.hh		diff \| blob \| history
src/arch/x86/isa/insts/arithmetic/add_and_subtract.py		diff \| blob \| history
src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py		diff \| blob \| history
src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py		diff \| blob \| history
src/arch/x86/isa/insts/compare_and_test/compare.py		diff \| blob \| history
src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py		diff \| blob \| history
src/arch/x86/isa/insts/compare_and_test/test.py		diff \| blob \| history
src/arch/x86/isa/insts/control_transfer/call.py		diff \| blob \| history
src/arch/x86/isa/insts/control_transfer/conditional_jump.py		diff \| blob \| history
src/arch/x86/isa/insts/control_transfer/jump.py		diff \| blob \| history
src/arch/x86/isa/insts/control_transfer/xreturn.py		diff \| blob \| history
src/arch/x86/isa/insts/data_conversion/sign_extension.py		diff \| blob \| history
src/arch/x86/isa/insts/data_transfer/conditional_move.py		diff \| blob \| history
src/arch/x86/isa/insts/data_transfer/move.py		diff \| blob \| history
src/arch/x86/isa/insts/data_transfer/stack_operations.py		diff \| blob \| history
src/arch/x86/isa/insts/data_transfer/xchg.py		diff \| blob \| history
src/arch/x86/isa/insts/load_effective_address.py		diff \| blob \| history
src/arch/x86/isa/insts/logical.py		diff \| blob \| history
src/arch/x86/isa/insts/processor_information.py		diff \| blob \| history
src/arch/x86/isa/insts/rotate_and_shift/rotate.py		diff \| blob \| history
src/arch/x86/isa/insts/rotate_and_shift/shift.py		diff \| blob \| history
src/arch/x86/isa/macroop.isa		diff \| blob \| history
src/arch/x86/isa/microasm.isa		diff \| blob \| history
src/arch/x86/isa/microops/ldstop.isa		diff \| blob \| history
src/arch/x86/isa/operands.isa		diff \| blob \| history
src/arch/x86/miscregfile.cc		diff \| blob \| history
src/arch/x86/process.cc		diff \| blob \| history
src/arch/x86/types.hh		diff \| blob \| history

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