Fixed wrong declaration in Verilog backend
authordh73 <dh73_fpga@qq.com>
Sun, 1 Oct 2017 16:11:32 +0000 (11:11 -0500)
committerdh73 <dh73_fpga@qq.com>
Sun, 1 Oct 2017 16:11:32 +0000 (11:11 -0500)
commite4808477531d31284244188637af3ccf89a21269
treeb2e1edce67aae3e692a521efda0df394d1347cbd
parentcbaba62401ca975bc9aee91b53e0b48fa59bd6c3
Fixed wrong declaration in Verilog backend
backends/verilog/verilog_backend.cc