git.libre-soc.org Git - openpower-isa.git/commit

author	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Sat, 24 Jul 2021 16:43:09 +0000 (17:43 +0100)
committer	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Sat, 24 Jul 2021 16:43:09 +0000 (17:43 +0100)
commit	e493511061a56e231a854d7dc2031755b0169251
tree	215fb827108a91610260cdab224a32c0392ba996	tree
parent	7073b3e9f127d97c00a06b658cce2b1fd12090cb	commit \| diff

added an extra SVP64 instruction, svstep, to replace setvl
"get end state" mode

openpower/isa/simplev.mdwn		diff \| blob \| history
openpower/isatables/RM-1P-1D.csv	[new file with mode: 0644]	blob
openpower/isatables/minor_22.csv		diff \| blob \| history
src/openpower/decoder/isa/caller.py		diff \| blob \| history
src/openpower/decoder/isa/test_caller_setvl.py		diff \| blob \| history
src/openpower/decoder/power_enums.py		diff \| blob \| history
src/openpower/sv/sv_analysis.py		diff \| blob \| history
src/openpower/sv/trans/svp64.py		diff \| blob \| history