git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Sun, 28 Oct 2018 15:24:07 +0000 (15:24 +0000)
committer	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Sun, 28 Oct 2018 15:24:07 +0000 (15:24 +0000)
commit	e50e079449d075cbfd047ce0139f00e639d1bca6
tree	f08a29629e851c82c2582248dde16f67b4bd1495	tree
parent	3c8427c8322f0cb331a6ecda5edf3e325ff37a82	commit \| diff

adjust mmu load to take reg_spec_t so that proper offset-adjustments can be made

the adding of the immediate plus the relevant offset to the relevant
register needs to be calculated before the load takes place. algorithm
is slightly different from the one used in rv_add

15 files changed:

riscv/insns/c_fld.h		diff \| blob \| history
riscv/insns/c_flw.h		diff \| blob \| history
riscv/insns/c_lw.h		diff \| blob \| history
riscv/insns/fld.h		diff \| blob \| history
riscv/insns/flq.h		diff \| blob \| history
riscv/insns/flw.h		diff \| blob \| history
riscv/insns/lb.h		diff \| blob \| history
riscv/insns/lbu.h		diff \| blob \| history
riscv/insns/ld.h		diff \| blob \| history
riscv/insns/lh.h		diff \| blob \| history
riscv/insns/lhu.h		diff \| blob \| history
riscv/insns/lw.h		diff \| blob \| history
riscv/insns/lwu.h		diff \| blob \| history
riscv/sv_mmu.cc		diff \| blob \| history
riscv/sv_mmu.h		diff \| blob \| history

Simple-V augmented version of spike

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