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(parent: e07b6d3) | patch
add a "SM" column into RM*.csv (and LDSTRM*.csv) identifying if MASK_SRC
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 17 Sep 2022 18:23:25 +0000 (19:23 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 17 Sep 2022 18:23:25 +0000 (19:23 +0100)
commite56281c5ce6df1641bf92b274ea30f10f2a76224
tree3033c913ce6227cce88b0b502ff469936df1b1dftree
parente07b6d381aaf16fac22ccff6d84a8d715cf62cfdcommit | diff
add a "SM" column into RM*.csv (and LDSTRM*.csv) identifying if MASK_SRC
is active.  this makes disassembly much easier, no need to check RM type
or count the number of registers
12 files changed:
openpower/isatables/LDSTRM-2P-1S1D.csv diff | blob | history
openpower/isatables/LDSTRM-2P-1S2D.csv diff | blob | history
openpower/isatables/LDSTRM-2P-2S.csv diff | blob | history
openpower/isatables/LDSTRM-2P-2S1D.csv diff | blob | history
openpower/isatables/LDSTRM-2P-3S.csv diff | blob | history
openpower/isatables/RM-1P-1D.csv diff | blob | history
openpower/isatables/RM-1P-1S.csv diff | blob | history
openpower/isatables/RM-1P-2S1D.csv diff | blob | history
openpower/isatables/RM-1P-3S1D.csv diff | blob | history
openpower/isatables/RM-2P-1S1D.csv diff | blob | history
openpower/isatables/RM-2P-2S1D.csv diff | blob | history
src/openpower/sv/sv_analysis.py diff | blob | history