Update state.pc on every instruction
authorAndrew Waterman <waterman@cs.berkeley.edu>
Thu, 26 Mar 2015 06:01:54 +0000 (23:01 -0700)
committerAndrew Waterman <waterman@cs.berkeley.edu>
Thu, 26 Mar 2015 06:03:16 +0000 (23:03 -0700)
commite5675bfcb3a8a798628317d6dccfbc9bd1ea3ebf
treeeeac812d700ab4f0e08d6e4ce0a99ae4137c587f
parent6c965e11dc7950207f7cc0baff0ff273c33f4ecc
Update state.pc on every instruction

This isn't a bug fix for Spike proper, but it makes it possible for
RoCC instructions to access the control thread's PC.
riscv/processor.cc