hdl.{ast,dst}: directly represent RTLIL default case.
authorwhitequark <whitequark@whitequark.org>
Tue, 25 Jun 2019 17:53:09 +0000 (17:53 +0000)
committerwhitequark <whitequark@whitequark.org>
Tue, 25 Jun 2019 22:01:14 +0000 (22:01 +0000)
commite5e23644a43581b912e8b6ce46f22a4934781c94
tree913ff7811cd8d7bb84f03ff49421f466c8c513ab
parentf60ceb349b1cb7439f85115d6fd255e56f30cd60
hdl.{ast,dst}: directly represent RTLIL default case.

This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase
nmigen/back/pysim.py
nmigen/hdl/ast.py
nmigen/hdl/dsl.py
nmigen/test/test_hdl_dsl.py