Fixed Verilog pre-processor for files with no trailing newline
authorClifford Wolf <clifford@clifford.at>
Tue, 29 Jul 2014 18:14:25 +0000 (20:14 +0200)
committerClifford Wolf <clifford@clifford.at>
Tue, 29 Jul 2014 18:14:25 +0000 (20:14 +0200)
commite605af8a4937533b35068071e14f5bd92c2e5b4f
treecd7348576a824d40b25a7891f0b3b0b339c49573
parent2145e57ef08784484e875e64cb43b6d1f4dbe50c
Fixed Verilog pre-processor for files with no trailing newline
frontends/verilog/preproc.cc