fpga/bram: Generate stall signal
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Sat, 19 Oct 2019 10:22:33 +0000 (21:22 +1100)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Wed, 30 Oct 2019 02:18:58 +0000 (13:18 +1100)
commite638c3e8ae9ca95c2dc5c831eb5fd7f72b173825
tree2d923ceaac44d2c506dcb421e6362f591edad0af
parent37acb35773e10f96907f6feda6a7c1922a5baf08
fpga/bram: Generate stall signal

This doesn't yet pipeline the block RAM, just generate a valid stall
signal so it's compatible with a pipelined master

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
fpga/mw_soc_memory.vhdl