divider: Always compute result/sresult/d_out.write_reg_data
authorPaul Mackerras <paulus@ozlabs.org>
Wed, 25 Sep 2019 10:03:46 +0000 (20:03 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Fri, 27 Sep 2019 22:41:17 +0000 (08:41 +1000)
commite6536d4b8bf93cdb5456b6cd97cfbc4ebc41f34c
tree71c3a9a604bf2946bad0f20c36ecaf8dd46001a7
parentad040601e6478a3fa4b9379c2d60183ab83235f5
divider: Always compute result/sresult/d_out.write_reg_data

These are intended to be combinatorial.  The previous code was giving
warnings in vivado about registers/latches with no clock defined.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
divider.vhdl