i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2)

i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2)

IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
so let's make use of it.

pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most
other things show less gains/no regressions, except furmark which
loses some 10 points.

I didn't have a BYT at hand for testing.

v2: Don't check (brw->gen == 7) in gen7 functions. (chadv)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>