i965: Flush the RC and TC before doing a fast clear resolve
authorKristian Høgsberg <krh@bitplanet.net>
Mon, 18 Aug 2014 19:31:14 +0000 (12:31 -0700)
committerKristian Høgsberg <krh@bitplanet.net>
Wed, 20 Aug 2014 00:21:39 +0000 (17:21 -0700)
commite6a53533b7aa790f66b044f77deaac450aa39fde
treea0f81915b9850e6e3d1b02960321815943cec482
parent8791cfeddeb13c31bce62c7a472712cb05d14aec
i965: Flush the RC and TC before doing a fast clear resolve

The docs say "When performing a render target resolve, PIPE_CONTROL with end
of pipe sync must be delivered.", which doesn't actually tell us whether we
need to do it before or after.  Blorp did it before and after, and doing it
before certainly makes sense.  The resolve operation needs to read from the
MCS and if we don't flush the render cache it won't get up-to-date data.

On the other hand, doing it after should not be necessary, since we call
brw_render_cache_set_check_flush() after the resolve.

Fixes rendering corruption in kwin's cover switch effect and various steam
games.

Missing flush spotted by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c