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(parent: f1f70a8) | patch
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
authorwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 04:22:16 +0000 (04:22 +0000)
committerwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 04:22:16 +0000 (04:22 +0000)
commite6cc3f72cf5620e90c2aebe24e995ed10b9c496c
tree09a4b1c48ace59dd3a2a7143e397e0d278c8737ctree
parentf1f70a8990b4cbc274d272f28a1714b613260b4fcommit | diff
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
examples/mem.py diff | blob | history
nmigen/back/verilog.py diff | blob | history
nmigen/hdl/mem.py diff | blob | history