Added module->design and cell->module, wire->module pointers
authorClifford Wolf <clifford@clifford.at>
Thu, 31 Jul 2014 12:11:39 +0000 (14:11 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 31 Jul 2014 12:11:39 +0000 (14:11 +0200)
commite6d33513a5b809facc6e3e5e75d2248bfa94f82b
treebcee5a22fc9ac7dca5b871ce667114e5f15d07d0
parent1cb25c05b37b0172dbc50e140fe20f25d973dd8a
Added module->design and cell->module, wire->module pointers
15 files changed:
frontends/ast/ast.cc
frontends/ilang/parser.y
frontends/liberty/liberty.cc
frontends/verific/verific.cc
kernel/rtlil.cc
kernel/rtlil.h
manual/PRESENTATION_Prog/Makefile
manual/PRESENTATION_Prog/my_cmd.cc
passes/abc/blifparse.cc
passes/cmds/copy.cc
passes/cmds/design.cc
passes/hierarchy/hierarchy.cc
passes/hierarchy/submod.cc
passes/sat/miter.cc
passes/techmap/extract.cc