i965: Make depth clear flushing more explicit
authorTopi Pohjolainen <topi.pohjolainen@intel.com>
Tue, 17 Jan 2017 09:44:52 +0000 (11:44 +0200)
committerTopi Pohjolainen <topi.pohjolainen@intel.com>
Wed, 18 Jan 2017 20:42:47 +0000 (22:42 +0200)
commite6da6943fed1228c551af1f0e1a405b6d67b41ae
treec540a53bba17d3e9f6cf35b18c8750dc68c77b40
parent4840a53e902b0f2b9841d9dbb90e479a3688153d
i965: Make depth clear flushing more explicit

Current blorp logic issues unconditional "flush everything"
(see brw_emit_mi_flush()) after each render. For example, all
blits issue this unconditionally which shouldn't be needed if
they set render cache properly so that subsequent renders do
necessary flushing before drawing.

In case of piglit:

ext_framebuffer_multisample-accuracy all_samples depth_draw small

intel_hiz_exec() is always preceded by blorb blit and the
unconditional flush looks to hide the lack of stall and flushes
in depth clears. By removing the brw_emit_mi_flush() I get gpu
hangs.

This patch adds the stalls and flushes mandated by the spec
and gets rid of those hangs.

v2 (Jason, Ken): Document the rational for separating
                 depth cache flush and stall on Gen7.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
src/mesa/drivers/dri/i965/brw_clear.c
src/mesa/drivers/dri/i965/gen8_depth_state.c