Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 29 May 2020 10:30:49 +0000 (11:30 +0100)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 29 May 2020 10:31:14 +0000 (11:31 +0100)
commite850669050e8cbb610b5b7f0b01a6d64790b9d74
tree6459e0eab990c5c21e30b21db31de9703ab4fbad
parent84e51164f8735aba19a1f8e2554f56d79a0d026e
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
8f/1c2e97ba7d6175f710bc28bfafd352d5b68208 [new file with mode: 0644]