vsx.md (vsx_concat_<mode>): Add support for the ISA 3.0 MTVSRDD instruction.
authorMichael Meissner <meissner@linux.vnet.ibm.com>
Fri, 12 Aug 2016 19:40:37 +0000 (19:40 +0000)
committerMichael Meissner <meissner@gcc.gnu.org>
Fri, 12 Aug 2016 19:40:37 +0000 (19:40 +0000)
commite86aefb8e955a9545ffd16c960ff70cbad5fc9ad
tree4d26a414fc4a986fb7a186ae3f68288ec0678c07
parentb1ad9be2e8170ead78f7522e7647111f3bc0dc6f
vsx.md (vsx_concat_<mode>): Add support for the ISA 3.0 MTVSRDD instruction.

[gcc]
2016-08-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

* config/rs6000/vsx.md (vsx_concat_<mode>): Add support for the
ISA 3.0 MTVSRDD instruction.
(vsx_splat_<mode>): Change cpu type of MTVSRDD instruction to
vecperm.

[gcc/testsuite]
2016-08-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

* gcc.target/powerpc/vec-init-1.c: New tests to test various
vector initialization options.
* gcc.target/powerpc/vec-init-2.c: Likewise.
* gcc.target/powerpc/vec-init-3.c: New test to make sure MTVSRDD
is generated on ISA 3.0.

From-SVN: r239428
gcc/ChangeLog
gcc/config/rs6000/vsx.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/powerpc/vec-init-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/powerpc/vec-init-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/powerpc/vec-init-3.c [new file with mode: 0644]