projects / openpower-isa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 80c5c65) | patch
add first functional confirmed unit test for parallel reduce REMAP
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 6 Sep 2022 14:50:35 +0000 (15:50 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 6 Sep 2022 14:50:35 +0000 (15:50 +0100)
commite88b945123f2c3f047748a44fdf446775517076a
tree2bbee8fad38f789b51bb9dd7e7859bac8a355387tree
parent80c5c65b2e24c0c813e18e118f79bc120ffbfb20commit | diff
add first functional confirmed unit test for parallel reduce REMAP
https://bugs.libre-soc.org/show_bug.cgi?id=864
using remap_preduce_yield directly, confirmed operational through ISACaller
added through decoder/isa/svshape.py which is responsible
in SVSHAPE.getiterator() for returning the appropriate yield-iterator
openpower/isa/simplev.mdwn diff | blob | history
src/openpower/decoder/isa/remap_preduce_yield.py diff | blob | history
src/openpower/decoder/isa/svshape.py diff | blob | history
src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py diff | blob | history