projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: d448483) | patch
write_verilog: dump $mem cell attributes.
authorwhitequark <whitequark@whitequark.org>
Thu, 6 Feb 2020 16:22:22 +0000 (16:22 +0000)
committerwhitequark <whitequark@whitequark.org>
Thu, 6 Feb 2020 16:22:42 +0000 (16:22 +0000)
commite95a8ba763999b9cce480a3aadf9fae206650f00
tree6fbe88d0c6614f26dca9e8dcfeffbe5bd8caf91btree
parentd44848328b329489eda0719968c3f81d4d9a6b55commit | diff
write_verilog: dump $mem cell attributes.

The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
backends/verilog/verilog_backend.cc diff | blob | history