projects / gram.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 44ff21c) | patch
replace the simulation Clock-Reset-Generator with one that is more general.
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 24 Feb 2022 17:55:05 +0000 (17:55 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 24 Feb 2022 17:55:05 +0000 (17:55 +0000)
commite9a4f8b13e75ae57429dc97f929b69e550b07c8e
treea5907c2e6265f46c7832b3f8ebd1fde08452cdbetree
parent44ff21cdbd27ca17ff0aa83ba337c57667bb950dcommit | diff
replace the simulation Clock-Reset-Generator with one that is more general.
the icarus verilog simulation now passes where previously it did not
gram/simulation/crg.py diff | blob | history