build.res,vendor: place clock constraint on port, not net, if possible.
authorwhitequark <whitequark@whitequark.org>
Thu, 6 Feb 2020 23:37:15 +0000 (23:37 +0000)
committerwhitequark <whitequark@whitequark.org>
Thu, 6 Feb 2020 23:37:15 +0000 (23:37 +0000)
commite9b4543aa5d3d65f1c67f583d5236371dfa33c33
tree253338c0a0efba9ab20aec6cd73c896ef9037575
parentbf5e4e20d936d085d5490ab6285ca0dcdaa528a3
build.res,vendor: place clock constraint on port, not net, if possible.

For most toolchains, these are functionally identical, although ports
tend to work a bit better, being the common case. For Vivado, though,
it is necessary to place them on the port because its timing analyzer
considers input buffer delay.

Fixes #301.
nmigen/build/res.py
nmigen/vendor/intel.py
nmigen/vendor/lattice_ecp5.py
nmigen/vendor/lattice_ice40.py
nmigen/vendor/lattice_machxo2.py
nmigen/vendor/xilinx_7series.py
nmigen/vendor/xilinx_spartan_3_6.py
nmigen/vendor/xilinx_ultrascale.py