RISC-V: Add address printer tests with ADDIW
authorTsukasa OI <research_trasio@irq.a4lg.com>
Sat, 27 Aug 2022 00:10:58 +0000 (00:10 +0000)
committerNelson Chu <nelson@rivosinc.com>
Fri, 2 Sep 2022 01:40:04 +0000 (09:40 +0800)
commite9f7ba21f08a264f813140eb6221e9d9670dc12f
treeda6e290e6ecd9ee120d1e87acbc3a2a877252f60
parent5edf42b635a375f7bf79e2079529eeb869129cbe
RISC-V: Add address printer tests with ADDIW

Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.

This commit tests whether this sign-extension works.

gas/ChangeLog:

* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address
computation with sign extension as used in ADDIW/C.ADDIW.
* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.
* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.

gas/ChangeLog:

* testsuite/gas/riscv/dis-addr-addiw-a.d: New test.
* testsuite/gas/riscv/dis-addr-addiw-b.d: New test.
* testsuite/gas/riscv/dis-addr-addiw.s: New test.
gas/testsuite/gas/riscv/dis-addr-addiw-a.d [new file with mode: 0644]
gas/testsuite/gas/riscv/dis-addr-addiw-b.d [new file with mode: 0644]
gas/testsuite/gas/riscv/dis-addr-addiw.s [new file with mode: 0644]