Simulation model verilog fix
authorMiodrag Milanovic <mmicko@gmail.com>
Wed, 26 Jun 2019 16:34:34 +0000 (18:34 +0200)
committerMiodrag Milanovic <mmicko@gmail.com>
Wed, 26 Jun 2019 16:34:34 +0000 (18:34 +0200)
commitea0b6258ab392b6186ee5d75a75da944b25d0392
tree17866fa26c6bed6f106709d9a14d4f3ebb14f482
parent0b7d648c6a71594f8a17e78aef8f62b6f6448390
Simulation model verilog fix
techlibs/ecp5/cells_sim.v
techlibs/xilinx/cells_sim.v