gdb/gdbserver: LoongArch: Improve implementation of fcc registers
authorFeiyang Chen <chenfeiyang@loongson.cn>
Tue, 2 Aug 2022 09:16:56 +0000 (17:16 +0800)
committerTiezhu Yang <yangtiezhu@loongson.cn>
Tue, 9 Aug 2022 14:22:23 +0000 (22:22 +0800)
commitea3352172ec868b821fa34b31ba8128bde735405
tree60452294ef7a7f9524a174b0c5fa1f2ddd5ac7b0
parenta88c79b77036e4778e70d62081c3cfd1044bb8e3
gdb/gdbserver: LoongArch: Improve implementation of fcc registers

The current implementation of the fcc register is referenced to the
user_fp_state structure of the kernel uapi [1].

struct user_fp_state {
uint64_t    fpr[32];
uint64_t    fcc;
uint32_t    fcsr;
};

But it is mistakenly defined as a 64-bit fputype register, resulting
in a confusing output of "info register".

(gdb) info register
...
fcc            {f = 0x0, d = 0x0}  {f = 0, d = 0}
...

According to "Condition Flag Register" in "LoongArch Reference Manual"
[2], there are 8 condition flag registers of size 1. Use 8 registers of
uint8 to make it easier for users to view the fcc register groups.

(gdb) info register
...
fcc0           0x1                 1
fcc1           0x0                 0
fcc2           0x0                 0
fcc3           0x0                 0
fcc4           0x0                 0
fcc5           0x0                 0
fcc6           0x0                 0
fcc7           0x0                 0
...

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/uapi/asm/ptrace.h
[2] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_condition_flag_register

Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
gdb/arch/loongarch.h
gdb/features/loongarch/fpu.c
gdb/features/loongarch/fpu.xml
gdb/loongarch-linux-tdep.c
gdb/loongarch-tdep.c
gdbserver/linux-loongarch-low.cc