litesata: update build core target generation
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 8 Apr 2015 22:00:25 +0000 (00:00 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 8 Apr 2015 22:00:25 +0000 (00:00 +0200)
commitea613cd8eef44c4f6048c7b58f3b6e6473008595
tree71fed19bd5c966124589990b3362e785de2b0f84
parent03aa972bb66b161dc2080aa4826f3c31251405ee
litesata: update build core target generation
misoclib/mem/litesata/example_designs/make.py
misoclib/mem/litesata/example_designs/platforms/verilog_backend.py