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(parent: ff1e850) | patch
i965: Switch mapping modes for non-explicit-flush blit-temporary maps.
authorEric Anholt <eric@anholt.net>
Tue, 25 Feb 2014 20:15:31 +0000 (12:15 -0800)
committerEric Anholt <eric@anholt.net>
Fri, 14 Mar 2014 19:56:21 +0000 (12:56 -0700)
commitea93246c009178b54848a7814a172164cd33d3c7
tree0e7ee83ba98781bf9cc72a81cce38365b7a3e13btree
parentff1e850eec7a18d2cc5984848977112f3c4ad4cfcommit | diff
i965: Switch mapping modes for non-explicit-flush blit-temporary maps.

On LLC, it should always be better to use a cached mapping than the GTT.
On non-LLC, it seems pretty silly to try to optimize read performance for
the INVALIDATE_RANGE_BIT case.  This will make the buffer_storage logic
easier.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/intel_buffer_objects.c diff | blob | history