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(parent: 2fc2f8a) | patch
fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 18 Mar 2015 13:58:40 +0000 (14:58 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 18 Mar 2015 13:59:22 +0000 (14:59 +0100)
commitea9c1b8e69a672b2bcdc8243a49ca7854f6c95b0
tree1b37ab64848cb416d4914dfcb7cf939c984065e1tree
parent2fc2f8a6c076658c024bfa785c5bbe30597b582bcommit | diff
fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"

This probably breaks simulation with Icarus Verilog (and others simulators?)
mibuild/generic_platform.py diff | blob | history
migen/fhdl/verilog.py diff | blob | history