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(parent: 1e942b9) | patch
hdl.{ast,dsl},back.rtlil: track source locations for switch cases.
authorwhitequark <cz@m-labs.hk>
Tue, 9 Jul 2019 19:18:02 +0000 (19:18 +0000)
committerwhitequark <cz@m-labs.hk>
Tue, 9 Jul 2019 19:26:47 +0000 (19:26 +0000)
commiteac8d8eaf923a8273288ec481f63310613c1a5c1
tree2181b71efb503074fce855ea63c8570387860fcatree
parent1e942b955f554f528f1721b94e0ccd194fbfd923commit | diff
hdl.{ast,dsl},back.rtlil: track source locations for switch cases.

This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff.
nmigen/back/rtlil.py diff | blob | history
nmigen/hdl/ast.py diff | blob | history
nmigen/hdl/dsl.py diff | blob | history
nmigen/hdl/xfrm.py diff | blob | history