hdl.mem: add DummyPort, for testing and verification.
authorwhitequark <cz@m-labs.hk>
Tue, 1 Jan 2019 03:08:10 +0000 (03:08 +0000)
committerwhitequark <cz@m-labs.hk>
Tue, 1 Jan 2019 03:08:10 +0000 (03:08 +0000)
commiteaef2e7d95202e8ce3ee06178299e57a1c2a3b37
tree5479a730b84c605a150e35ae31e38d390addc879
parent4394854ba6b4663c414eef99fd33e74557bee9f7
hdl.mem: add DummyPort, for testing and verification.
nmigen/hdl/mem.py
nmigen/test/test_hdl_mem.py