arch-riscv: Move standard ops out of ISA
authorAlec Roelke <ar4jc@virginia.edu>
Tue, 7 Nov 2017 19:15:41 +0000 (14:15 -0500)
committerAlec Roelke <ar4jc@virginia.edu>
Wed, 29 Nov 2017 00:55:46 +0000 (00:55 +0000)
commiteb02066b31c85d22c67d1ead61048c196653ba1f
tree1ab43820091dcf702bf2e7ed083eb27bd3cfb313
parentd3ecb5d406a3dc12c53a20c271db3027b8477c39
arch-riscv: Move standard ops out of ISA

This patch removes static portions of the standard instruction types
from the generated ISA code and puts them into arch/riscv/insts. Some
dynamically-generated content is left behind for each individual
instruction's implementation. Also, BranchOp is removed due to its
similarity with ImmOp and ImmOp and UImmOp are joined into a single
templated class, ImmOp<T>.

Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
Reviewed-on: https://gem5-review.googlesource.com/6022
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
src/arch/riscv/insts/SConscript
src/arch/riscv/insts/bitfields.hh [new file with mode: 0644]
src/arch/riscv/insts/standard.cc [new file with mode: 0644]
src/arch/riscv/insts/standard.hh [new file with mode: 0644]
src/arch/riscv/isa/formats/compressed.isa
src/arch/riscv/isa/formats/standard.isa
src/arch/riscv/isa/includes.isa