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(parent: 93830a4) | patch
whoops vloop continuation logic the wrong way round
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 1 Oct 2018 11:00:27 +0000 (12:00 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 1 Oct 2018 11:00:27 +0000 (12:00 +0100)
commiteb0c1339c3339f51744e01e548a3091ff9c056fa
treea31c1ac2a95644cd28f3311331d338e51bb50abatree
parent93830a4ba370d50a15b72d0d30b8ef7b055f78aecommit | diff
whoops vloop continuation logic the wrong way round

the loop has to continue if there is one vectorised register left
rather than stop if there is *no* vectorised registers
riscv/insn_template_sv.cc diff | blob | history
riscv/sv.cc diff | blob | history
riscv/sv_decode.h diff | blob | history
Simple-V augmented version of spike