verilog: fix specify src attribute
authorEddie Hung <eddie@fpgeh.com>
Mon, 4 May 2020 17:53:06 +0000 (10:53 -0700)
committerEddie Hung <eddie@fpgeh.com>
Mon, 4 May 2020 17:53:06 +0000 (10:53 -0700)
commiteb5eb60fd4af431ea38a50ad1deebcc40ad4c222
tree7115f9042aa94798283a091633b760ad56e6769f
parent584780d776c92bc91731dbc2710dd8d9a624dc70
verilog: fix specify src attribute
frontends/verilog/verilog_parser.y
tests/various/specify.ys