test: add initial (minimal) test for clock abstraction modules.
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 13 Mar 2020 11:24:36 +0000 (12:24 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 13 Mar 2020 11:38:23 +0000 (12:38 +0100)
commiteb9f54b2bca60c416f929acb40c7c5f7db1335d8
tree8e49708af04499bc93fda20f6eb5383181944ea4
parentc304c4db27dfc01d05a96eb9c3e1aa63c27fc0de
test: add initial (minimal) test for clock abstraction modules.

Also fix divclk_divide_range on S6DCM.
litex/soc/cores/clock.py
test/test_clock.py [new file with mode: 0644]