Remove some FPGA style signal inits
authorAnton Blanchard <anton@linux.ibm.com>
Tue, 7 Jun 2022 10:01:14 +0000 (20:01 +1000)
committerAnton Blanchard <anton@ozlabs.org>
Tue, 7 Jun 2022 10:01:14 +0000 (20:01 +1000)
commitebdddcc402cc9a15499876c4a43fd1f559be56b4
tree21acc5cf551cbc80fb0df482e67a784f68d9212e
parenta750365ffa5f07046256d2824520817a6f704214
Remove some FPGA style signal inits

These don't work on the ASIC flow, so remove them and initialise
them explicitly where required.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
spi_flash_ctrl.vhdl
spi_rxtx.vhdl