projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 1b113a0) | patch
Use ABC to convert AIGER to Verilog, then sat against Yosys
authorEddie Hung <eddie@fpgeh.com>
Fri, 7 Jun 2019 18:05:36 +0000 (11:05 -0700)
committerEddie Hung <eddie@fpgeh.com>
Fri, 7 Jun 2019 18:05:36 +0000 (11:05 -0700)
commitebe29b66593414d0317879359d1f1d1f61a9ecc4
treeafcc4b47234b312bf52e58e2f5662dfaed392fcatree
parent1b113a05742377f5b18d52bc5bf50b1991e88c19commit | diff
Use ABC to convert AIGER to Verilog, then sat against Yosys
tests/aiger/run-test.sh diff | blob | history