projects / riscv-isa-sim.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 3fd738a) | patch
On misaligned fetch, set EPC to target, not branch itself
authorAndrew Waterman <aswaterman@gmail.com>
Sat, 3 Jan 2015 01:29:05 +0000 (17:29 -0800)
committerAndrew Waterman <aswaterman@gmail.com>
Sat, 3 Jan 2015 01:29:05 +0000 (17:29 -0800)
commitec297672b0c9d58d1ee6c2ac976ccf28863bd3c2
tree3ddc58262ddca8b2f610cff9e53bf4390a989d8ctree
parent3fd738af16ef977f1aa507e2525bb4c16fff9026commit | diff
On misaligned fetch, set EPC to target, not branch itself
riscv/decode.h diff | blob | history
riscv/insns/jal.h diff | blob | history
riscv/insns/jalr.h diff | blob | history
riscv/mmu.h diff | blob | history
Simple-V augmented version of spike