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(parent: 4451f7f) | patch
backend/verilog: Add alternate mode for transparent read port output.
authorMarcelina Kościelnicka <mwk@0x04.net>
Tue, 25 May 2021 21:42:58 +0000 (23:42 +0200)
committerMarcelina Kościelnicka <mwk@0x04.net>
Sun, 1 Aug 2021 17:11:29 +0000 (19:11 +0200)
commitec2a468bd389a8275a9a2584fb475901cc495d03
tree40a3283653f1fe41e51a1fd61fc41dc329537f15tree
parent4451f7f5e9b451a7885259554cd3e9562bbf8f88commit | diff
backend/verilog: Add alternate mode for transparent read port output.

This mode will be used whenever read port cannot be handled in the
"extract address register" way, ie. whenever it has enable, reset,
init functionality or (in the future) mixed transparency mask.
backends/verilog/verilog_backend.cc diff | blob | history