projects / gcc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b91dfdc) | patch
re PR target/70341 (cost model for addresses is incorrect, slsr is using reg + reg...
authorJakub Jelinek <jakub@redhat.com>
Wed, 27 Feb 2019 18:11:26 +0000 (19:11 +0100)
committerJakub Jelinek <jakub@gcc.gnu.org>
Wed, 27 Feb 2019 18:11:26 +0000 (19:11 +0100)
commitec3029103841b4298baff9adc37bfa7d357bdbe3
tree636854c51d3ea41c6d1a20d708107d22812d05edtree
parentb91dfdcc68b96c399c3815f7700f1803eea34972commit | diff
re PR target/70341 (cost model for addresses is incorrect, slsr is using reg + reg + CST for arm)

PR target/70341
* config/aarch64/aarch64.md (casesi): Create the casesi_dispatch
MEM manually here, set MEM_READONLY_P and MEM_NOTRAP_P on it.

From-SVN: r269260
gcc/ChangeLog diff | blob | history
gcc/config/aarch64/aarch64.md diff | blob | history