dcache: Fix bug in store hit after dcbz case
authorPaul Mackerras <paulus@ozlabs.org>
Fri, 15 May 2020 12:01:02 +0000 (22:01 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Fri, 15 May 2020 12:01:02 +0000 (22:01 +1000)
commiteca0fb5bf1950043c4f424fd2dfc4f64694a728b
tree31b72ba546e71b29aadf23a5461c6ea371b4c017
parent941499133e74eb786a27ea84e430f87af2c6f511
dcache: Fix bug in store hit after dcbz case

This fixes a bug where a store that hits in the dcache immediately
following a dcbz has its write to the cache RAM suppressed (but not
its write to memory).  If a load to the same location comes along
before the cache line gets replaced, the load will return incorrect
data.

Fixes: 4db1676ef8b3 ("dcache: Don't assert on dcbz cache hit")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
dcache.vhdl