dcache: Rework RAM wrapper to synthetize better on Xilinx
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Mon, 25 May 2020 06:48:47 +0000 (16:48 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 2 Jun 2020 09:56:08 +0000 (19:56 +1000)
commitecaa5e2fb28e08650ea51936f3018cf5cec32c58
tree38c91402dc4982da20e010dc1d0f6f9081555563
parenta9178ed0c151e6096e378777f31739556e0eeb9b
dcache: Rework RAM wrapper to synthetize better on Xilinx

The global wr_en signal is causing Vivado to generate two TDP (True Dual Port)
block RAMs instead of one SDP (Simple Dual Port) for each cache way. Remove
it and instead apply a AND to the individual byte write enables.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
cache_ram.vhdl
dcache.vhdl
icache.vhdl